Amit K. Varshney 7420 Seneca Falls Loop Phone: (+1-512) 301-9963 Austin TX 78739-2217 Email: amitkv@yahoo.com USA URL : http://amitkv.tripod.com/ EDUCATION MS Computer Engg., University of Minnesota, Minneapolis, MN Graduation date: June 2000, GPA: 3.827/4.000 B.Tech. Electrical Engg. (minor: Computer Sc.), Indian Institute of Technology, Kanpur, India Graduation date: May 1996, GPA: 8.7/10.0 WORK EXPERIENCE - 01/06/20 - Present: Intel Corporation, Austin, TX. - 09/05/17 - 12/31/19: Samsung Austin R&D Center, Austin, TX. - 07/10/00 - 09/01/17: Intel Corporation, Austin, TX. - 01/16/00 - 07/09/00: Research Assistance, University of Minnesota, Minneapolis, MN. - 09/16/98 - 06/13/99, 09/04/99 - 01/15/00: Teaching Assistance, University of Minnesota, Minneapolis, MN. - 06/14/99 - 09/03/99: Internship (software development), Cadence Design Systems, New Providence, NJ (an engineering center of Cadence Design Systems, Inc., San Jose, CA). Designed and implemented glitch and delay analysis tool using concepts of timing window and clock constraints. Language of work: C++. - 06/18/96 - 07/31/98: Software Development. Member of Technical Staff, Cadence Design Systems, Noida, India (an engineering center of Cadence Design Systems, Inc., San Jose, CA). Job responsibilities: Development of Logic Work Bench (LWB), Analog Work Bench (AWB) and related Cadence tools in the Systems Simulation area. Programming languages used: C, C++, VC++. - (team of two) development of verilog and VHDL flows in the Cadence Performance Engineering flow. This work involved development in VC++ on Windows NT. - (team of two) development of Analog Work Bench (AWB, the analog design, simulation and testing environment of Cadence). - (team of four) development and maintenance of Logic Work Bench (LWB, the multi-engine digital simulation tool of Cadence). - During work at Cadence, gained in-depth understanding of the development cycle of subparts of products. Got acquainted with the quality processes and software engineering practices as per the ISO 9000 standards and necessary for software development, and adhered to them myself. - Trainings/workshops attended: Compiler Construction, Software Engg, Operating Systems, C++, VC++, Windows Programming, Windows Operating System Concepts, UI Design for Usability, EDA, Presentation and Assertiveness for Communication Effectiveness, Managing Personal Growth, Managing Time for Results. INDUSTRY PUBLICATIONS - Paper in an Intel internal design and test technology conference (August 2007, team of 5), on an in-house developed formal property distribution and management methodology, tools and flows, and its use in a microprocessor project. - Paper in an Intel internal design and test technology conference (August 2006, team of 3, main author), on an in-house developed scan methodology, tools and flows for a microprocessor project. - Paper in an Intel internal design and test technology conference (August 2004, team of 4), on an in-house developed full-chip formal verification methodology, tools and flows for a microprocessor project. EXPERTISE - Programming Languages/ Paradigms: C, C++, Java, Visual C++, Pascal, Fortran, Windows programming, Motif, perl, JavaScript, HTML, lex, yacc, assembly languages of Dec-alpha and Intel's 80x86 family of processors, Oracle8.0 SQL. - HDLs: Verilog, VHDL, Hspice. - Operating Systems: Unix, Windows, Dos. - Platforms: Sun Sparc family, Intel's Pentium family, HP PA-9000, IBM RS-6000, Dec Alpha, Intel's 80x86 family. - CAD Tools: Cadence (Logic Work Bench, Analog Work Bench, Concept Schematic Generator, VHDL/Verilog Netlister, Hierarchy Manager, Allegro, Leapfrog), Mentor Graphics, Viewlogic Logic Simulator, Leonardo Synthesizer and Editor, Magic, Cypress Warp, Hspice, IBM Testbench. - Miscellaneous: Mercury Xrunner UI Test Automation Tool, Knowledge of ISO processes. TECHNICAL COURSEWORK - Taken during graduate study: Introduction to Algorithm Design, Operating Systems, Internet Programming, The Principles of Database Systems, Advanced Computer Networks, Advanced Computer Architecture, VLSI CAD Lab, VLSI Design, Applied Switching Theory, Advanced Topics in Design Automation: Advances in Specification, Synthesis and Performance Analysis of Embedded Systems, Graph Theory. - Taken during undergraduate study: Data Structures, Computer Organization, Advanced Computer Architecture, VLSI System Design, Digital Switching, Digital Communication Networks, Queueing Systems, Image Processing, Electronic Instrumentation, Communication Systems, Digital Signal Processing, Microprocessor Technology, Principles of Communication, Signals, Systems and Networks. ACADEMIC PROJECTS, RESEARCH AND PUBLICATIONS - Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt and Brion Keller, "High Performance Parallel Fault Simulation," in proceedings, IEEE International Conference on Computer Design, 2001, pp. 308-313. - Power Management for Multiprocessor Systems Using Stochastic Modeling, as part of coursework in Design Automation. - Designed and implemented an 8x8 ATM Switching Network in hardware. - Experimental study of benchmarks (SPEC-2000) used to compare performance of computer architectures, by simulating the benchmark programs on architectures with varying parameters, and gathering statistics, as part of coursework in Advanced Computer Architecture. The benchmarks used for study were in the research phase when we worked on them. - Designed and implemented features in Nachos (an experimental operating system developed at UC Berkeley) as part of coursework in Operating Systems. - Designed and implemented an HTTP server as part of coursework in Internet Programming. - Final year undergraduate B.Tech. project (1995-96), "Hierarchical Pattern Recognition and Noise Reduction using Wavelet and Wavelet Packet Transforms". - R.K.Malik, K.Subramanian and A.Varshney, "Matched-Filter analysis of large scale structures in the first CfA slice," International Conference on Gravitation and Cosmology, Dec 95, Inter University Center for Astronomy and Astrophysics (IUCAA), Pune, India. HONORS, AWARDS AND RECOGNITION - Goodie Drawer Level II Award (June 2011) at Intel, from a design flows infrastructure engineer, for getting central formal verification automated flows up and running for a new remote site project. - Goodie Drawer Level II Award (May 2011) at Intel, from a design manager, for jumping into an extremely time-critical project stepping on a short notice and providing timely formal equivalence verification support. - Goodie Drawer Level II Award (April 2011) at Intel, from a design automation manager, for a knowledge sharing presentation to the larger design automation team, on formal formal verification concepts, tools, flows and challenges. - Design Automation Excellence Award (February 2011) at Intel, for development, project customization and performance fine-tuning of, and sustained effort in execution and debug support of RTL Formal Property Verification in a CPU project, leading to the discovery of a critical silicon bug. - Goodie Drawer Level II Award (February 2011) at Intel, from a smartphone silicon-on-chip senior IP designer, for formal verification debug help to him and his team. - Goodie Drawer Level II Award (February 2011) at Intel, from a smartphone silicon-on-chip design project leader, for final formal verification database audits, increasing the confidence in quality of tapeout design data. - Goodie Drawer Level II Award (January 2011) at Intel, from a chipsets validation engineer, for help in direction with formal property verification flow for his project. - Goodie Drawer Level II Award (January 2011) at Intel, from a central runs infrastructure engineer, for establishing fully automated push-button formal verification flow for a new CPU project stepping, on a new platform, on a very short notice. - Goodie Drawer Level II Award (December 2010) at Intel, from a hardware design integration engineer, for enabling and customizing a new full-chip formal verification flow for integration of a complex CPU project, and for providing critical support for its execution during all milestones of the project, enabling them to complete the milestones on time and with high quality and confidence. - Goodie Drawer Level II Award (September 2010) at Intel, from a hardware design engineer, for help in verification and debugging a big and complex array circuit design. - Design Automation Excellence Award (August 2010) at Intel, for timely driving of verification convergence of a low power CPU core design, at regular sync points. This enabled timely downstream design cycle activities on healthy design database. - Service Award (July 2010) at Intel, for completing 10 years at Intel. - Goodie Drawer Level II Award (July 2010) at Intel, from a hardware design engineer, for driving methodology for central formal verification push-button runs for a new IP, independent of SOCs in which the IP fits. - Goodie Drawer Level II Award (June 2010) at Intel, from a hardware design manager, for preparing and delivering a customized training on formal verification for a significant milestone of a complex CPU project. - Goodie Drawer Level II Award (June 2010) at Intel, from a hardware design integration engineer, for enabling full-chip formal verification flow for integration of a complex CPU project. - Goodie Drawer Level II Award (May 2010) at Intel, from a methodology manager, for an urgent debugging of a critical design failure. - Goodie Drawer Level II Award (May 2010) at Intel, from a hardware design team, for delivering a critical connectivity verification functionality in a tool at a very short notice. - Goodie Drawer Level II Award (April 2010) at Intel, from a hardware design engineer, for help in verification and debugging a big and complex array circuit design. - Goodie Drawer Level II Award (April 2010) at Intel, from a hardware design engineer, for customized training and help in debugging a big and complex array circuit design. - Goodie Drawer Level II Award (April 2010) at Intel, from a hardware design engineer, for preparing and delivering a training (with lab) on formal verification tools, flow and methodology to a new project team (of about 40 people). - Goodie Drawer Level II Award (January 2010) at Intel, from a hardware design engineer, for helping establish a new RLS formal verification methodology, for a new CPU project. - Goodie Drawer Level II Award (April 2009) at Intel, from a hardware design engineer, for helping formally debug and verify a critical and complex System-on-Chip design, which led his group to meet a significant milestone in the design cycle of the project. - Goodie Drawer Level I Award (February 2009) at Intel, from a hardware design engineer, for helping formally verify several critical and complex clock designs while also working around a siginificant tool bug, enabling the design team to meet a significant milestone in the design cycle of the project. - Plaque (October 2008) at Intel, for significant contributions to the first platform launch of the Intel Atom processor. - Goodie Drawer Level II Award (September 2008) at Intel, from a standard cells library group manager, for working with the standard cells library team to improve the quality of a major cells library stream, to make it production worthy in a short time, for a time-critical low-power architecture microprocessor project. - Kudos Award (September 2008) at Intel, from a hardware design engineer, for helping formally verify a design in an unusual mode of formal verification and in a complex flow environment. - Kudos Award (September 2008) at Intel, from a hardware design engineer, for helping formally verify several critical and challenging designs and making timely bug fixes and enhancements in the flows to enable that. - Kudos Award (August 2008) at Intel, from a hardware design team manager of another design project, for helping formally verify a critical and challenging design. - Kudos Award (August 2008) at Intel, from the group manager, for developing and delivering a high quality training for a new formal verification flow in a low-power architecture microprocessor project. - Kudos Award (July 2008) at Intel, from a standard cells library group manager, for interviewing candidates and providing feedback, for a strategic position in the standard cells library team. - Kudos Award (July 2008, team of 1) at Intel, from a hardware design engineer, for successfully debugging a critical hardware design problem. - Kudos Award (April 2008, team of 1) at Intel, from a hardware design engineer, for successfully debugging a critical hardware design problem. - Kudos Award (March 2008, team of 1) at Intel, from a hardware design engineer, for successfully debugging a critical hardware design problem. - Kudos Award (January 2008, team of 12) at Intel, from a senior manager, for contribution to the development of a new CPU IP. - Kudos Award (December 2007, team of 1) at Intel, from a senior technical manager, for presenting an international internal conference paper in which I was a co-author, to a local audience. - Kudos Award (July 2007, team of 1) at Intel, from a hardware design engineer, for successfully debugging a hardware design compilation failure in his design, in a microprocessor project. - Kudos Award (June 2006, team of 1) at Intel, from a customer team (a DFT validation engineering team at Intel), for developing DFT chain walking tools, which led to finding bugs and keeping RTL healthy in a microprocessor project. - Kudos Award (January 2006, team of 1) at Intel, from a customer (a DFT engineer at Intel), for developing DFD scanout insertion and stitching tools, which enabled flawless execution of scanout insertion in the whole chip of a microprocessor project. - Service Award (July 2005) at Intel, for completing 5 years at Intel. - Kudos Award (October 2004, team of 1) at Intel, from a customer (a hardware design and validation engineer at Intel), for helping in logic synthesis and compilation (for formal verification) of a design containing a mix of verilog and VHDL code, through a mix of internal and external tools. - Kudos Award (October 2004, team of 1) at Intel, from a customer (a hardware design engineer at Intel), for delivering a 1-day long class (with labs) on formal verification and its tools. - Kudos Award (September 2004, team of 1) at Intel, from a customer (a hardware design engineer at Intel), for a study on capabilities of an internal sequential verification tool. - Plaque (July 2004) at Intel, for significant contribution to a complex microprocessor project. - Kudos Award (March 2004, team of 1) at Intel, from a fellow design automation engineer at another Intel site (Folsom, CA), for fixing a critical bug in an RTL compilation tool, at a critical time of a microprocessor project. - Kudos Award (December 2003, team of 2) at Intel, from a customer (a hardware design engineer at Intel), for helping debug formal verification failures of his and his hardware design team's designs during a critical phase of a microprocessor project. - Kudos Award (November 2003, team of 1) at Intel, from a fellow design automation engineer at another Intel site (Folsom, CA), for enhancing an internal RTL compilation flow during a critical phase of a microprocessor project. The enhancement resulted in a speedup of 2-3x in compile time when some blocks are blackboxed. - Kudos Award (September 2003, team of 2) at Intel, from a customer (a hardware design engineer at Intel), for helping in formal verification of his and his hardware design team's designs during a critical phase of a microprocessor project. - Kudos Award (August 2003, team of 3) at Intel, from a customer (a hardware design engineer at Intel), for helping in formal verification of his and his hardware design team's designs during a critical phase of a microprocessor project. - Kudos Award (April 2003, team of 2) at Intel, for formal verification support at a critical phase of a microprocessor project. - Kudos Award (February 2003, team of 1) at Intel, from a customer (a circuit design engineer at Intel), for helping in formal verification of his design. - Kudos Award (June 2002, team of 2) at Intel, for design methodology support to a microprocessor project's circuit library. - Kudos Award (May 2002, team of 2) at Intel, for enabling formal verification of library cells (rtl vs schematic) and development of alternate library views, and verification plus debugging support to circuit designers, in a high pressure (dungeon) environment. - Kudos Award (May 2002, team of 11) at Intel, for enabling circuit library cells creation and verification. - Kudos Award (May 2002, team of 3) at Intel, from a customer (a circuit design engineer at Intel), for helping in logic extraction of schematics view of the customer's design and formal verification of the extracted model against abstract RTL, using Intel's internal tools. - Kudos Award (April 2002, team of 2) at Intel, for evaluating a new internal logic extraction tool. - Kudos Award (December 2001, team of 1) at Intel, from a customer (a circuit design engineer at Intel), for helping in logic extraction of schematics view of the customer's design and formal verification of the extracted model against abstract RTL, using Intel's internal tools. - Kudos Award (November 2001, team of 2) at Intel, from another customer (circuit design engineer at Intel), for the same activities as above but for a different design. - Kudos Award (November 2001, team of 2) at Intel, from another customer (circuit design engineer in another team at Intel), for the same activities as above but for a different design. - Spontaneous Recognition Award (November 2001, team of 5 - cross-functional and multi-site, divided between US and Israel) at Intel, for evaluating and productizing a logic extraction and formal equivalence verification tools flow. - Kudos Award (August 2001, team of 3) at Intel, for the same. - Kudos Award (December 2000, team of 5) at Intel, for evaluation, experimentation and comparative study of three formal equivalence verification tools. - Team Award (June 1998, team of 4) at Cadence, for contributing to software development of a simulation flow, filling a significant gap in the Cadence PCB design flow. - National Talent Search Scholarship (1990-96). Stood FIRST in Rajasthan (my homestate), India, in the preliminary screening exam of the selection process. - Certificate of Merit (1991) in National Mathematics Olympiad, conducted by Govt of India for selection in the Indian team for International Mathematics Olympiad. Stood SIXTH (top 0.1%) in Rajasthan (my homestate), India. - Special award by the Governor of Rajasthan (my homestate) in India for standing FIFTH (top 0.01%) of around 50,000 candidates in the state engineering entrance examination (1992). - Certificate of Merit (1992) in National Physics Olympiad. Stood among top 100 (top 0.5%) at national level of around 25,000 candidates from all over India. - Certificate of Merit (1992) in National Science Talent Search Examination. Stood among top 100 (top 0.5%) at national level of around 20,000 candidates. - Stood among top 0.5% of around 100,000 candidates in Joint Entrance Examination (1992) of the Indian Institutes of Technology, the premier Science and Technology institutes of India. - Awarded silver medals for four years for performance in National Talent Search Contest in Mathematics. EXTRA CURRICULAR ATTAINMENTS - Member of Emergency Response Team at Intel Austin site, 2007 - 2010. The team regularly undergoes trainings, exercises, drills and case studies to maintain preparedness to handle any kind of emergency at the site. Was also a backup leader of the team and covered for the leader for a few days in 2009. - Kudos Award (October 2002, team of 6) at Intel, for winning the first prize (scored the most points) of 5 teams at scavenger hunt, a team-building fun event. Was team leader of this (winning) team of 6. - Volunteer in Intel's community involvement events during 2000. - Secretary, Industrial Exhibitions, Techkriti 1996 (Annual All-India Technology Fair of IIT Kanpur). Was also involved in fund-raising activities for the fair. - Secretary, Photography, for all institute level events of IIT Kanpur during 1994-95. - Member, National Service Scheme (N.S.S., a social service scheme of the government of India), 1992-93. - Member, school band, 1985-86.